An Accurate and Stochastic-Based Approach to Timing-Driven Partitioning and Placement

We present an accurate new approach to timing-driven partitioning and placement that is particularly suited to deep submicron technology, and to the large circuits that are implemented on such chips. We present rationale for why iterative-improvement based partition-driven placement should be the approach of choice for optimizing any objective like timing, power and area. We establish desirable characteristics for the nodegain function of such a placement approach for timing minimization, and then show how previous techniques have been deficient in them. These drawbacks are remedied in our proposed approach, which is expected to be faster and more effective than current techniques. The speed increase will derive partly from the fact that our method is partition-driven, which, being a divide-and-conquer technique, is much faster than numerical or statistical (e.g., simulated annealing) methods. Our technique’s increased effectiveness will result from our more accurate modeling of net connectivity and delay, and a node gain formulation that is directly related to minimizing the maximum path delay and that incorporates futuristic stochastic information. Finally, while formulating our new timing-driven approach, we also establish some results using the Elmore-delay model on good placement and routing of nets for minimizing the interconnect delays to their most-critical sink nodes.